In recent years it has been seen that the complexity and density of very large scale integrated circuit designs has increased manyfold. As a result of this, it has become increasingly important to establish the reliability of this type circuitry.
Many of the present day large scale integrated circuit desings have been implemented with error detection circuits, such as parity generation and parity checking circuits. Such types of circuits are often designated as CED (concurrent error detection) circuits. Many of the systems in the prior art do detect errors by the use of conventional error-checking circuits and then will often inform a maintenance processor of the error. To a great extent, however, the error-related information obtained is very limited and sufficient information cannot be obtained unless the entire scan path is analyzed.
The system presented here is applicable to VLSI designs where a scan path is utilized. In a chip, flip-flops are connected to each other to form one or more long shift registers. Those long shift registers are also designated as a shift chain, snake or scan path.
The purpose of implementing snakes in a VLSI design is to minimize the maintenance controller interface signals. All the data, for example, chip initialization data, are shifted (written) into the snakes through an SDI, serial data input, or shifted out (read from) the snakes through an SDO, serial data output, in serial form.
The objective of the present system is to sample the outputs of the concurrent error detection (CED) circuits and to collect sufficient error information for a maintenance controller to analyze the error data under normal operating conditions and not merely under specialized error checking conditions.
Thus, it is an objective of this system to provide circuits in a VLSI device together with an error log and analysis mechanism which can operate without disrupting the normal operation of the system for one set of faults, and further to generate a signal to freeze the VLSI circuit for another type of faults, in order to prevent erroneous data from being propagated into other modules.
Additionally, the system of this disclosure operates to provide circuitry that will provide exhaustive self-test of the concurrent error detection (CED) circuits and to provide a structured and expandable error logging and reporting circuit system for the large scale integrated chip.